| ISBN: ISSN: 0923-8174
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| ISBN: DOI: 10.1023/A:1008374811502
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| |
| description |
An efficient deterministic BIST scheme based on partial scan chains
together with a scan selection algorithm tailored for BIST is
presented. The algorithm determines a minimum number of flipflops to
be scannable so that the remaining circuit has a pipeline-like
structure. Experiments show that scanning less flipflops may even
decrease the hardware overhead for the on-chip pattern generator
besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.
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| publisher |
Springer Netherlands
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| type |
Text
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| Article in Journal
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| source |
In: Journal of Electronic Testing - Theory and Applications (JETTA).
Vol. 16(3), pp. 169-177
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| contributor |
Rechnerarchitektur (IFI)
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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| deterministic scan-based BIST
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| partial scan
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